The structure of an EEPROM memory cell with a single level of gate conductor, which is frequently constituted by a polycrystalline silicon layer (single poly) though it may also be constituted by an aluminum or aluminum alloy layer, may be schematically depicted as the structure of a MOS transistor, commonly an n-channel, isolated-gate transistor, wherein the control terminal is capacitively coupled to the isolated gate. The isolated gate is fundamentally and physically contoured over two zones: a thin tunnel-oxide zone, through which the basic electrical phenomena of the writing and erasing mechanisms of the memory cell occur, and a relatively thicker oxide zone, over which the isolated gate acts as the gate of a "read" transistor for reading the state or the data stored in the memory cell.
This typical structure of the known art, is depicted schematically in FIGS. 1, 2 and 3. See, for example, U.S. Pat. No. 4,935,790 incorporated herein by reference. The isolated gate 1 lies over a programming first active area 2 of the semiconducting substrate in order to form a capacitive coupling zone between the same isolated gate 1 and a control terminal 3. The isolated gate 1 has a first projection 1t and a second projection 1l, both extending over a second active area 4. In this second active area, the relative diffusions for creating a "read", n-channel, MOS transistor are formed, the drain terminal (contact) of which being indicated with 5 and the source region with 6 in the figure. Also in this second active area 4 the capacitive coupling between the isolated gate structure with a zone 7 of the semiconducting substrate which is covered with a thin, dielectric, tunnelling layer, essentially thinner than the dielectric gate layer which is present over the rest of the area 4, is realized. Moreover, as shown in FIGS. 1 and 2, within the same second active area 4, an n-channel select transistor is also commonly formed, the gate of which is indicated with 8 and the relative control terminal with 9 (FIG. 1) and whose source terminal is indicated with 10.
The fact that the gate 1l of the "read" transistor is formed on the same active area 4 over which the writing/erasing gate 1t is also formed, creates precise limitations and nonnegligible drawbacks. In these known cells, relatively low voltages must be maintained across the "read" gate of the cell, i.e. between the source and the drain regions (6 and 5) of the read transistor of the cell, in order to prevent an unintentional modification of the programmed or erased state of the memory cell. In fact, by being the read transistor's gate 1l formed within the same active area 4 of the write/erase tunnelling zone 7, any voltage across these regions is replicated in the write/erase gate zone and this voltage determines an electric field across the tunneling thin dielectric layer 7 given by: ##EQU1##
If not appropriately limited, this electric field may determine a reverse voltage value sufficient to program an erased cell or to erase a programmed cell, thus causing erroneous responses of the memory device.
These restraints on the voltage levels which may be safely used in reading the data stored in the memory cell, i.e. of the voltage levels which may be used at the interface of the memory cell toward the external circuitry, disadvantageously limit the use of the memory cell as a modular element capable of being coupled directly with other CMOS structures of the circuitry outside the memory section of the integrated circuit. On the contrary, this makes necessary to operate with relatively small amplitude signals and to add signal level regenerating stages "downstream" of the EEPROM cells, thus increasing the signal propagation times and the power consumption of the integrated circuit.